OffCourse Verilog
Worked out solutions to the verilog VPL assignments in the PEC on https://moodle.feitsma.uk
Logic Gates A
Mars Exploration
mars_exploration.v Download!
Expand Hidemodule REF(
input clk,
input enable,
input reset,
input measure,
output reg sample,
output reg error
);
localparam IDLE = 3'd0, MOVING = 3'd1, MEASURE = 3'd2, ERROR = 3'd3, DONE = 3'd4;
reg [2:0]state;
reg [2:0]state_next;
reg [1:0]repeats;
always @(posedge clk) begin
if (reset || state_next == IDLE) begin
sample <= 0;
error <= 0;
state <= IDLE;
repeats <= 0;
end else if (state_next == MEASURE) begin
state <= state_next;
repeats <= repeats + 1;
end else if (state_next == DONE) begin
state <= state_next;
sample <= 1;
end else if (state_next == ERROR) begin
state <= state_next;
error <= 1;
end else begin
state <= state_next;
end
end
always @(*) begin
case (state)
IDLE: begin
if(enable) begin
state_next = MOVING;
end
end
MOVING: begin
if (!enable) begin
state_next = IDLE;
end else if (measure && enable) begin
state_next = MEASURE;
end else begin
state_next = state;
end
end
MEASURE:
if(!enable) begin
state_next = IDLE;
end else if (!measure && repeats < 3) begin
state_next = DONE;
end else if (!measure && repeats == 3) begin
state_next = ERROR;
end else begin
state_next = MEASURE;
end
DONE:
if (reset || !enable) begin
state_next = IDLE;
end else begin
state_next = DONE;
end
ERROR:
if (reset || !enable) begin
state_next = IDLE;
end else begin
state_next = ERROR;
end
endcase
end
endmodule
Rat Race
rat_race.v Download!
Expand Hidemodule REF (
input clk,
input lever,
input world_crisis,
input inheritance,
input [2:0] amount,
output reg [5:0]money
);
always @(posedge clk) begin
if (world_crisis) begin
money <= 5'd0;
end else if(inheritance) begin
money <= money + amount + 1;
end else if(lever) begin
money <= money + 1;
end else
money <= money;
end
endmodule