module uart_parity_even(
    input reset,
    input signal,
    input clk,
    
    output reg valid,
    output reg error
);


localparam BREAK = 0,
IDLE = 1,
START = 2,

B1E = 3,
B1O = 4,

B2E = 5,
B2O = 6,

B3E = 7,
B3O = 8,

B4E = 9,
B4O = 10,

PO = 11,
PE = 12,

SO = 13, 
SE = 14;


reg [3:0] state;
reg [3:0] state_next;

always @(posedge clk) begin
    if (reset) begin
        state <= BREAK;
        valid <= 0;
        error <= 0;
    end else begin
        error <= 0;
        valid <= 0;
        case (state_next)
            SO: error <= 1;
            SE: valid <= 1;
        endcase
        state <= state_next;
    end
end


always @(*) begin
    case (state)
        BREAK: begin
            case (signal)
                1: state_next = IDLE;
                default: state_next = BREAK;
            endcase
        end
        IDLE: begin
            case (signal)
                1: state_next = IDLE;
                default: state_next = START;
            endcase
        end
        START: begin
            case (signal)
                1: state_next = B1O;
                default: state_next = B1E;
            endcase
        end
        
        B1E: begin
            case (signal)
                1: state_next = B2O;
                default: state_next = B2E;
            endcase
        end
        B2E: begin
            case (signal)
                1: state_next = B3O;
                default: state_next = B3E;
            endcase
        end
        B3E: begin
            case (signal)
                1: state_next = B4O;
                default: state_next = B4E;
            endcase
        end
        B4E: begin
            case (signal)
                1: state_next = PO;
                default: state_next = PE;
            endcase
        end
        
        B1O: begin
            case (signal)
                1: state_next = B2E;
                default: state_next = B2O;
            endcase
        end
        B2O: begin
            case (signal)
                1: state_next = B3E;
                default: state_next = B3O;
            endcase
        end
        B3O: begin
            case (signal)
                1: state_next = B4E;
                default: state_next = B4O;
            endcase
        end
        B4O: begin
            case (signal)
                1: state_next = PE;
                default: state_next = PO;
            endcase
        end
        
        PO: begin
            case (signal)
                1: state_next = SO;
                default: state_next = BREAK;
            endcase
        end
        PE: begin
            case (signal)
                1: state_next = SE;
                default: state_next = BREAK;
            endcase
        end
        
        SO: begin
            case (signal)
                1: state_next = IDLE;
                default: state_next = START;
            endcase
        end
        SE: begin
            case (signal)
                1: state_next = IDLE;
                default: state_next = START;
            endcase
        end
        
        
    endcase 

end

endmodule