module counter_fsm (
    input clk,
    input complete,
    input enable,
    input reset,
    
    output reg [1:0] repeats,
    output reg trigger
);

localparam IDLE = 0,
    COUNTING = 1,
    DONE = 2,
    PAUSED = 3;

reg [3:0] state, state_nxt;



always @(posedge clk) begin
    if(reset) begin
        state <= IDLE;
        repeats <= 0;
        trigger <= 0;
    end else begin
        state <= state_nxt;
        repeats <= state_nxt == IDLE ? 0 : (state_nxt == DONE ? (repeats + 1) : repeats);
        trigger <= state_nxt == DONE;
    end
end


always @(*) begin
    
    case(state)
        //IDLE
        default: begin
            if(complete)
                state_nxt = IDLE;
            else
                state_nxt = enable ? COUNTING : PAUSED;
        end
        
        COUNTING: begin
            if(enable) begin
                state_nxt = complete ? DONE : COUNTING;
            end else
                state_nxt = complete ? IDLE : PAUSED;
        end
        
        DONE: begin
            if(complete) begin
                state_nxt = enable ? DONE : IDLE;
            end else
                state_nxt = enable ? COUNTING : PAUSED;
        end
        
        PAUSED: begin
            if(enable) begin
                state_nxt = complete ? DONE : COUNTING;
            end else
                state_nxt = complete ? IDLE : PAUSED;
        end
    endcase
end

endmodule