module counter (
    input clk,
    input reset,
    input enable,
    input valid,
    
    input [4:0] value,
    
    output trigger,
    output reg [4:0] count,
    output [1:0] repeats
);

counter_fsm FSM1 (
    .clk(clk),
    .complete(count == 0),
    .enable(enable),
    .reset(reset),
    
    .repeats(repeats),
    .trigger(trigger)
);

always @(posedge clk) begin
    if(reset) begin
        count <= 0;
    end else if(valid)
        count <= value;
    else if(count != 0 && enable)
        count <= count - 1;
    else
        count <= count;
end

endmodule